Semiconductor devices such as microprocessors and memory devices employ solid state transistors as a basic, primary operational structure of the integrated circuits thereof. One type of transistor commonly employed in semiconductor structures and devices is the field effect transistor (FET), which generally includes a source contact, a drain contact, and one or more gate contacts. A semiconductive channel region extends between the source contact and the drain contact. One or more pn junctions are defined between the source contact and the gate contact. The gate contact is located adjacent at least a portion of the channel region, and the conductivity of the channel region is altered by the presence of an electrical field. Thus, an electrical field is provided within the channel region by applying a voltage to the gate contact. Thus, for example, electrical current may flow through the transistor from the source contact to the drain contact through the channel region when a voltage is applied to the gate contact, but may not flow through the transistor from the source contact to the drain contact in the absence of an applied voltage to the gate contact.
Recently, field-effect transistors (FETs) have been developed that employ discrete, elongated channel structures referred to as “fins.” Such a transistor is often referred to in the art as a “finFET.” Many different configurations of finFETs have been proposed in the art.
The elongated channel structures or fins of a finFET comprise a semiconductor material that may be doped either n-type or p-type. It has also been demonstrated that the conductivity of n-type doped semiconductor materials may be improved when the n-type semiconductor material is in a state of tensile stress, and the conductivity of p-type semiconductor materials may be improved when the p-type semiconductor material is in a state of compressive stress.
U.S. Pat. No. 8,169,025, which issued May 1, 2012 to Bedell et al., discloses a semiconductor device and fabrication method that include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin.